The map of leading-edge semiconductor manufacturing is unusually concentrated. Roughly 90 % of all chips at the 5 nm node and below are fabricated in Taiwan, with the remainder split between South Korea and a single Intel site in Arizona. The 2022 US CHIPS and Science Act earmarked $52 B in subsidies and tax credits to break that concentration — but two and a half years in, what's actually shifted, and what hasn't?
What the money actually bought
The headline beneficiaries are Intel (Ohio fab cluster), TSMC (Arizona), Samsung (Texas), and Micron (New York). Combined commitments exceed $300 B in private capex against the $52 B in federal subsidies — a ~6× private-to-public ratio that's politically defensible but economically tight when fab cost overruns routinely run 30–80 %.
The visible failures are equally instructive. TSMC Arizona slipped from a 2024 to a 2025 production target, then again. Skilled-trade availability — pipefitters, welders, electricians familiar with Class-1 cleanroom construction — became the binding constraint, not capital. Taiwan's strength was never just a TSMC monopoly; it was an entire industrial ecosystem of suppliers, technicians, and tacit knowledge that doesn't ship in shipping containers.
Why physical geography still pins the industry
Three factors keep concentration intact even when subsidies are abundant:
- Water. A leading-edge fab consumes 4–10 million gallons per day of ultrapure water. Arizona drought conditions and the Colorado River basin allocations make this a non-trivial siting question.
- Power stability. EUV lithography is exquisitely sensitive to grid voltage variation. Taiwan's grid is purpose-engineered around its fabs.
- Talent density. A single fab needs ~1,500 engineers and ~3,000 technicians. The ecosystem-effect of having ten fabs in a 50 km radius makes hiring and retention work; one isolated fab is structurally disadvantaged.
What to watch next
The ASML High-NA EUV systems that begin shipping in volume in 2026–2027 will reset the leading-edge frontier. Whoever installs and qualifies them first will hold the next process-node lead through about 2030. Today the answer is still Taiwan and Korea by a comfortable margin; the CHIPS-funded US sites are aiming to qualify second-generation EUV (low-NA), not the new High-NA tools, in their first production runs.
Geopolitically, the more subtle effect is the rise of compatible-but-not-identical nodes — slightly different process recipes that produce chips usable for the same applications but not directly interchangeable. This makes strategic stockpiling harder and creates leverage points downstream in design and packaging.